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TB1305FG, tb1308fg 2007-07-11 1 toshiba bicmos integrated circuit silicon monolithic TB1305FG,tb1308fg component sw, sync separation and h/v frequency counter ic for tvs the TB1305FG and tb1308fg include a component sw block, a prefilter for ad conversion, sync separation and h/v format detectors for tv component video signals. the TB1305FG and tb1308fg contribute to reduction in the proportion of pcb occupied by lcr filters and to the simplification of designs on analog interfaces. the TB1305FG and tb1308fg are equipped with an i 2 cbus interface through which various functions can be controlled. features component block ? component video input: TB1305FG 2 channels, tb1308fg 3 channels; rgb available ? component video output ? gain switching: 0db / +6db ? bandwidth filter: prefilter for adc; 4.2 to 31mhz variable) sync separation block ? supports 525/60i/60p, 625/50i/50p, 750/50p/60p, 1125/50i/60i/50p/60p, 1250/50i, vga @60, svga@60, xga@60, sxga@60, uxga@60 ? hd/vd input: 2 channels; positive and negative input acceptable ? hd/vd output: positive and negative output selectable ? masking pseudo-sync for copyguard signal others ? line detector for d-pin (2 channels) ? horizontal and vertical frequency counter ? format detection circuit for input signal ? automatic sync process switching mode lineup part no. number of component video inputs TB1305FG 2 tb1308fg 3 p-qfp48-1014-0.80 weight: 0.83 g (typ.)
TB1305FG, tb1308fg 2007-07-11 2 block diagram sync-out line3 det ycbcr sw sync tip /bias bias bias bias bias h/v sep iicbus +6db amp mute v sep pol sync tip /bias sync tip clamp cr1/r1-in line3-1 cb1/b1-in line2-1 y1/g1-in line1-1 nc sync1-in sw line2 cr2/r2-in line3-2 cb2/b2-in line2-2 y2/g2-in vd2-in hd2-in address vd-out hd-out h vcc y-out h gnd cb-out vf0adj cr-out nc (sync3-in) +6db amp mute +6db amp mute band width ycbcr sw ycbcr sw band width band width sync tip clamp sync sw pol line2 det line1 det iicbus sw det bias bias h-c/d v-c/d freq count dummy sync sync sw note: pins 38, 39, 41 and 43 are available for the tb1308fg only. the pins are nc for the TB1305FG. the TB1305FG and tb1308fg do not support weak signals, ghost signals or other non-standard signals. some functional blocks, circuits or constants may be omitted or simplified in the block diagram for explanatory purposes.
TB1305FG, tb1308fg 2007-07-11 3 pin functions the equivalent circuit diagrams may be simplified or some parts of them may be omitted for explanatory purposes. pin no. pin name function interface circuit input signal/output signal 22 dig v cc v cc pin for the logical circuits. supply power through a resistor from pin 31 like the application circuit. this pin voltage is clipped to 3.3 v (typ.) by the internal regulator. 22 31 33 500 50 50 3.3v 3.3 v (typ.) 20 dig gnd gnd pin for the logical circuits. ? ? 31 h v cc v cc pin for the sync circuits. connect 5.0 v (typ.) ? 5.0 v (typ.) 33 h gnd gnd pin for the sync circuits. ? ? 46 c v cc v cc pin for the video circuits. connect 5.0 v (typ.) ? 5.0 v (typ.) 44 c gnd gnd pin for the video circuits. ? ? 5 14 39 y1/g1-in y2/g2-in y3/g3-in y or g input pin. input the signal via a clamp capacitor. the clamp system is selectable by clamp register. note: pin 39 is not available for the TB1305FG. it is an nc pin. sync tip level: 2.1 v (typ.) bias level: 2.7 v (typ.) rgb/ycbcr/ypbpr signal amplitude: 0.7 vp-p (without sync) 47 y-in y or cvbs input pin. input the y or cvbs signal in ntsc, pal or secam from an av-sw via a clamp capacitor. the clamp system is selectable by clamp register. 46 44 5 14 (39) 47 2.9v/1.5v 200 200 12k 200 100k 2.8v sync tip level: 2.1 v (typ.) bias level: 2.7 v (typ.) y/cvbs signal?s amplitude: 1.0 vp-p (with sync) 1 3 10 12 43 41 cr1/r1-in cb1/b1-in cr2/r2-in cb2/b2-in cr3/r3-in cb3/b3-in cb/cr, pb/pr or b/r input pin. input the signal via a capacitor. note: pins 41 and 43 are not available for the TB1305FG. they are nc pins. 200 46 44 12k 200 100k 1 3 10 12 (43) (41) 2.8v 2.7 v bias (typ.) rgb/ycbcr/ypbpr signal amplitude: 0.7 vp-p (without sync) 45 c-in chroma signal input pin. input c signal from av-sw via a capacitor. when this pin?s voltage is high, test mode for shipping is active. the pin voltage must be less than 3.6 v during operating. 45 46 44 200 1.5v 30.2k test c 1.7 v bias (typ.) prohibited 3.6v 0v 5v 1.7v (typ) 8 16 38 sync1-in sync2-in sync3-in composite sync input pin to separate into h- and v-sync. input the signal via a resister and a clamp capacitor. note: pin 38 is not available for the TB1305FG. it is an nc pin. 31 33 8 16 (3 8) 10k sync tip level: 1.75 v (typ.) 1vp-p or 1vp-p
TB1305FG, tb1308fg 2007-07-11 4 pin no. pin name function interface circuit input signal/output signal 24 26 hd1-in hd2-in hd input pin. input a separated horizontal sync signal (1.0 to 2.0 vp-p) via a resister and a coupling capacitor. the polarity of the input signal is detected and its leading edge becomes a timing trigger. 23 25 vd1-in vd2-in vd input pin. input a separated vertical sync signal (1.0 to 2.0 vp-p) via a resister and a coupling capacitor. the polarity of the input signal is detected and its leading edge becomes a timing trigger. 22 200 20 23 24 25 26 1.45 v bias (typ.) or 6 15 line1-1 line1-2 line1 (number of lines) detection pin. connect line1 of d-pin. dc 2 11 line3-1 line3-2 line3 (aspect ratio) detection pin. connect line3 of d-pin. 46 1k 44 th1 th2 10k 20k 20k 2 6 11 15 200 150k dc 4 13 line2-1 line2-2 line2 (i/p) detection pin. connect line2 of d-pin. dc 48 9 sw line1 sw line2 sw line detection pin. connect sw line of d-pin. 46 1k 44 10k 40k 4 9 13 48 200 150k dc 32 y-out y, g or cvbs signal output pin. 34 cb-out cb, pb, b or c signal output pin. 36 cr-out cr, pr or r signal output pin. 46 44 32 34 36 100 ac: 0 db or +6 db (typ.) 28 sync-out separated composite sync output pin. 0.1v(typ.) 3.4v(typ.) 29 30 vd-out hd-out hd or vd output pin. the polarity of the output is selectable by hv-pol register. the tailing edge of the vd-out has a jitter. use the leading edge only. 31 33 3.3k 28 29 30 100 250 0.1v(typ.) 3.4v(typ.) or 0.1v(typ.) 3.4v(typ.) 17 42 dac1 dac2 1-bit dac output pin. open-collector pin. 31 33 17 42 100 100 dac test dc
TB1305FG, tb1308fg 2007-07-11 5 pin no. pin name function interface circuit input signal/output signal 21 xtal crystal connection pin. connect a 3.579545 mhz crystal for ntsc demodulation to generate internal clocks. 21 31 33 500 2.5k ? 35 vf0adj a filter pin to adjust bandwidth filter characteristics. 35 46 44 200 200 ? 40 bias fil a filter pin for internal bias circuits. 40 46 44 800 1k 1k ? 18 sda sda pin for i 2 cbus. 18 20 31 50 5k ack sda 22 th: 2.25v(typ.) th: 1.50v(typ.) h to l: 1.50 v (typ.) l to h: 2.25 v (typ.) 19 scl scl pin for i 2 cbus. 19 20 31 5k 22 th: 2.25v(typ.) th: 1.50v(typ.) h to l: 1.50 v (typ.) l to h: 2.25 v (typ.) 27 address slave address switching pin. connect to 5 v vcc or gnd. or leave this pin open. 27 46 44 th1 th2 10k 20k 20k 40 60k 1k 5 v vcc: dc h /dd h open: da h /db h gnd: d8 h /d9 h 7 37 nc these pins are not used. connect to gnd. note: pins 38, 39, 41 and 43 of the TB1305FG are not used . connect them to gnd. ? ?
TB1305FG, tb1308fg 2007-07-11 6 bus control map write mode slave address: d8 h / da h / dc h sa d7 d6 d5 d4 d3 d2 d1 d0 preset 00 mute ? filpass hd width dac2 dac1 ycbcr sw gain 00000000 01 f0 sw bandwidth 00000000 02 fc half sync sw hv freq 00000000 03 hv-sep vga-sep 1( ps mask ) a sync s mode clamp hv-pol vd phs 00000000 note: set ps mask = 1 (on) for except ?sync on g? input. remark: sa = sub-address. read mode slave address: d9 h / db h / dd h d7 d6 d5 d4 d3 d2 d1 d0 0 line1 line2 line3 sw line1 sw line2 ? 1 hd-pol vd-pol h format v format 2 h fm2 v fm2 h in v in v-sync-w ? version 3 ? v freq det 4 h freq det ? : undefined
TB1305FG, tb1308fg 2007-07-11 7 bus control functions write mode register name function preset value mute swtches mute mode. 0: normal 1: video mute normal (0) filpass switches the bandwidth limit filter. 0: on (by-pass) 1: off on (0) hd width switches the width of hd-out. 0: wide 1: narrow remark: hd width = 1 (narrow) is recommended for the 1125/50p/60p format owing to crosstalk from hd-out to video signals so that spike noises on video signals will occur. wide (0) dac1,2 1-bit dac switching output voltages of dac1 (pin 17) and dac2 (pin 42) are controlled. dac1/2 are open-collector pins. 0: low (on) 1: high (open) low (0) ycbcr sw switches the component video input and line input 00: y1 / cb1 / cr1 / line1, 2, 3-1 (pins 1, 2, 3, 4, 5, 6) 01: y2 / cb2 / cr2 / line1, 2, 3-2 (pins 10, 11, 12, 13, 14, 15) 10: y / c (pins 45, 47. cr-out is muted.) 11: y3 / cb3 / cr3 (pins 39, 41, 43) note: the data (11) is not available for the TB1305FG. y1 / cb1 / cr1 (00) gain switches the output gain. gain of ycbcr output (pins 32, 34, 36) is controlled. 0: 0 db 1: + 6 db remark: gain = 0 (0 db) is recommended for the 1125/50p/60p format since this offers superior frequency characteristics to those of +6 db mode. 0 db (0) f0 sw switches the f0 of bandwidth limit filter 0: high 1: low high (0) bandwidth switches the f0 of bandwidth limit filter 0000000: min (low) 1111111: max (high) min (0000000) fc half switches the frequency of bandwidth limit filters for cb/cr the cutoff frequency of bandwidth limit filters for cb/cr is 1/2 to y. 0: off (same for 3 outputs) 1: on (1/2 fc for cb/cr) off (0)
TB1305FG, tb1308fg 2007-07-11 8 register name function preset value switches sync input. sync input to hd/vd-out and to sync-out is selected. hd out (pin 30) vd out (pin 29) sync out (pin 28) 000 sync1 (pin 8) 001 sync2 (pin 16) 010 sync3 (pin 38: tb1308fg only) 011 not available 100 hd1 (pin 24) vd1 (pin 23) sync1 (pin 8) 101 hd2 (pin 26) vd2 (pin 25) sync2 (pin 16) 110 hd1 (pin 24) vd1 (pin 23) sync3 (pin 38 : tb1308fg only) 111 hd2 (pin 26) vd2 (pin 25) sync3 (pin 38: tb1308fg only) sync sw note: sync3 of the data 010, 110, 111 is not available for the TB1305FG. sync1 (000) hv freq input format setting set the horizontal and vertical mode according to the format that is input. 0000: 15.625 khz, 50 hz (625i) 0001: 15.75 khz, 60 hz (525i) 0010: 31.25 khz, 50 hz (625p) 0011: 31.5 khz, 60 hz (525p, vga@60hz) 0100: 28.125 khz, 50 hz (1125/50i) 0101: 33.75 khz, 60 hz (1125/60i) 0110: 37.5 khz, 50 hz (750/50p) 0111: 45 khz, 60 hz (750/60p, xga@60hz) 1000: 31.25 khz, 50 hz (1250i) 1001: 37.9 khz, 60 hz (svga@60hz) 1010: 64 khz, 60 hz (1125/60p, sxga@60hz) 1011: 75 khz, 60 hz (uxga@60hz) 1100: 56.25 khz, 50 hz (1125/50p) 1101 ~ 1111: not available 15.625 khz, 50 hz (0000) hv-sep switches the separation level. the h/v sync separation level to sync-in (pins 8, 16, 38) is switched. 0: low 1: high remark: the separation level is changed according to the ratio of negative sync width per h period and the connected resistance. low (0) vga-sep switches the separation level. the h/v sync separation level to sync-in (pins 8, 16, 38) is switched for pc signals. 0: normal (component video) 1: vga remark: the separation level is changed according to the ratio of negative sync width per h period and the connected resistance. normal (0) ps mask switches the mask mode for pseudo-sync. pseudo-syncs in lines are removed. 0: off (v-blk period only) 1: on (all lines) note: set ps mask = 1 (on) for except ?sync on g?. off (0)
TB1305FG, tb1308fg 2007-07-11 9 register name function preset value a-sync automatic sync processing mode. sync processing mode is changed in accordance with the results obtained by the internal format detection circuits. format detection is performed for a sync or hd/vd signal selected by sync sw. the result of detection is returned to h, v format and h, v fm2. the hv freq setting is invalid when this mode is active. 0: off (manual switching mode by hv freq setting) 1: on off (0) s mode switches sync output mode. this function sets the dummy hd/vd output mode when there is no input. the frequency of the dummy hd/vd output depends on the hv freq setting (when a-sync = off) or h, v format (when a-sync = on). h, v in shows whether there is no input or not. 0: off (no hd and free-run vd output (approx. 44 hz), when there is no input. however, in 1250i mode, no hd and no vd output, when there is no input.) 1: on (dummy hd/vd output when there is no input) off (00) clamp switches y clamping mode. this function sets the clamping mode for pins 5, 14, 39. 0: sync tip clamp 1: bias sync tip (0) hv-pol switches the polarity of the hd/vd output. this function sets the polarity of hd/vd out (pins 29, 30). 0: positive 1: negative positive (0) vd phs switches the phase of dummy vd output. vd phs compensates for delay time so that the dummy vd-out phase is the same as that form the separated v-sync. 0: no delay 1: 0.2 h delay (0.15 h delay for 1125/50p) no-delay (0) read mode register name function line1 line1 detection for d-pin (for the number of lines) 00: 525 (480) 01: 750 (720) 10: ---- 11: 1125 (1080) detects the voltage of line1 selected by ycbcr sw. 11 is returned when the pin is not connected. line2 line2 detection for d-pin (for i/p) 0: interlace 1: progressive detects the voltage of line2 selected by ycbcr sw. 1 is returned when the pin is not connected. line3 line3 detection for d-pin (for aspect ratio) 00: 4:3 01: 4:3 letter box 10: ---- 11: 16:9 detects the voltage of line3 selected by ycbcr sw. 11 is returned when the pin is not connected. sw line1 sw line1 (pin 48) detection for d-pin 0: connected 1: not connected sw line2 sw line1 (pin 9) detection for d-pin 0: connected 1: not connected hd-pol polarity detection to hd-in 0: positive 1: negative detects the width from the hd-in pin to determine whether it is negative or not. when the high level of the input hd-in is wider than approx 14 s, hd-pol shows 1.
TB1305FG, tb1308fg 2007-07-11 10 register name function vd-pol polarity detection to vd-in 0: positive 1: negative detects the width from the vd-in pin to determine whether it is negative or not. when the high level of the input vd-in is wider than approx 4.5 ms, vd-pol shows 1. h format horizontal format detection 0000: 15.625/15.75khz 0001: 28.125khz 0010: 31.25/31.5khz 0011: 33.75khz 0100: 37.5/37.9khz 0101: 45/48khz 0110: 64khz/67.5khz 0111: 75khz 1000 56.25khz 1001 ~ 1111: undefined detects a horizontal format (horizontal frequency). note1: format detection errors such as the following can occur when suppressed syncs are input. see note3 in the function description on automatic sync processing mode, too. 525i input 525p detected, 625i input 625p detected, 1125i input 1125p detected 525p/625p input no v-sync detected note2: when 525i, 625i, 1125/50i or 1125/60i signal is input, h format data can be incorrect caused by the pseudo-syncs for copy guard or the equalizing pulses. v format vertical format detection 00: 50 hz 01: 60 hz 10 ~ 11: undefined detects a vertical format (horizontal frequency) according to v freq det data. h fm2 horizontal format detection 2 0: known 1: unknown detects whether an input is in one of the defined formats or not. this is based on h format data. note: h fm2 may indicate unknown, when 525p input with pseudo sync signal for copy guard is input. v fm2 vertical format detection 2 0: known 1: unknown detects whether an input is in one of the defined formats or not. this is based on v format data. h in input detection to horizontal syncs 0: no signal 1: signal v in input detection to vertical syncs 0: no signal 1: signal v-sync-w v-sync width detection 0: wide 1: narrow detects v-sync width for detecting 1250i format. under a-sync = 1 (on), v-sync-w shows 1, when the vd width from the vd-in pin is narrower than approx 69 s, or when the v-sync width from the sync-in pin is narrower than approx 27 s. version ic version identification 00: TB1305FG 01: tb1308fg 10: ---- 11: ---- v freq det counts the vertical frequency of an input selected by sync sw. 0000000: over 3.5khz 1001111: 44hz or less 1010000 1111111: no signal how to calculate a vertical frequency (y): convert data read from v freq det into decimal value and call it x. vertical frequency (y) = 1 (x 2.8607 10 -4 ) [hz] the error range of x is ? 1 to + 1. h freq det counts the horizontal frequency of an input selected by sync sw. 00000000: no signal 11111111: over 85khz how to calculate a horizontal frequency (y): convert data read from h freq det into decimal value and call it x. horizontal frequency (y) = 1 (0.003 x) [hz] the error range of x is ? 1 to + 1.
TB1305FG, tb1308fg 2007-07-11 11 note 1: in determining the decision algorithms (detection range, detection times and so on) for h/v frequency detection, it is necessary to take into account both previously mentioned cautions and other factors such as signal conditions and i 2 cbus data transmission in the course of prototype tv set evaluation. note 2: the read bus flags indicate that a certain signal is detected at a given moment. however, the detection result will not be very reliable if only one flag is checked. to obtain accuracy, it is recommended that a judgment will be made on the basis of confirming several times and verifying agreement among the majority of flags read in a sequence and/or at the same time.
TB1305FG, tb1308fg 2007-07-11 12 function descriptions vertical sync separation for 1250i/50 when hv freq = 1000, the vertical sync separation for 1250i/50 is accomplished through the use of a special circuit. the phase of the vd-out (pin 29) depends on the h-sync timing shown in the figure below. there is no vd-out when there is no h-sync input. in the manual sync processing mode (a-sync = off), use read bus functions, v-sync-w and h, v format (or h, v freq det) to detect 1250i/50. note: the vd-out?s tailing edge has a jitter. use the leading edge only. hd width hd-out width is selectable by hd width, as below. hd width = 1 (narrow) is recommended for the 1125/50p/60p format owing to crosstalk from hd-out to vide o signals so that spike noises on video signals will occur. sync-in (y-in) hd-out (hd width=1) hd-out (hd width=0) 1.65us (typ) 0.65us (typ) 1125/60p signal
TB1305FG, tb1308fg 2007-07-11 13 automatic sync processing mode (a-sync) counted horizontal and vertical frequency data to input signal are returned to read bus functions, h, v freq det. also, the detected format is returned to h, v format and h, fm2 when the h/v frequencies are in internal defined ranges. input detection results, which indicate whether there is an input or not, for h, v-sync or hd, vd are returned to h, v in. in automatic sync processing mode (when a-sync = on), the TB1305FG and tb1308fg operate as indicated in the following table according to these read data. input condition h, v format status h, v fm2 status h, v in status hd, vd outputs standard format the format as input known signal the separated sync as input non-standard format the status indicates not the current condition but the last detected format. unknown signal the separated sync as input no input the status indicates not the current condition but the last detected format. known: the status indicates not the current condition but the last detected format. no signal dummy hd and vd, of which the frequency depends on the h, v format status note 3: the following format detection errors can occur when suppressed syncs are input. 525i input 525p detected, 625i input 625p detected, 1125i input 1125p detected 525p/625p inputs in case of the 525p/625p sync amplitude become bigger from zero to its standard gradually, v-sync of the input is not detected even though the sync amplitude is got back to its standard amplitude. the v-sync separation performance to the suppressed sync input may be improved when vga-sep is set to 1 (vga), though the h and v separation level are also changed. note 4: we recommend recognizing a format by h/v freq det rather than one by h/v format because h format and h fm2 can indicate an incorrect data for 525i, 625i, 525p, 1125/50i and 1125/60i caused by the pseudo-syncs for copy guard or the equalizing pulses. note 5: dummy hd and vd may become unstable while the mode is changing from one format to another. by the way, in a-sync = off and s-mode = on mode, dummy hd and vd are output according to hv freq setting when there is no input. manual sync processing mode (a-sync = off *note6 ) hv freq = 625p is required to separate h-sync and v-sync properly. set hv freq = 625p to count h/v-sync for manual sync processing mode. the following is an example of how to detect h/v frequency when a-sync=off. 1. set hv freq = 625p(0010) and read data such as h, v freq det. 2. detect the h/v frequencies by microprocessor or similar means, depending on the data obtained. 3. set hv freq and so on to the detected mode. 4. continue to monitor the obtained data such as h, v freq det. when any alteration is recognized, set hv freq = 625p(0010) and detect again. decision algorithms (for detection range, detection times and so on) for h/v frequency detection should be determined taking into account the above-mentioned errors in measuring h/v frequencies and the other factors such as signal conditions and i 2 cbus data transmission in the course of prototype tv set evaluation. note 6: we recommend recognizing formats for 525i and 625i signals by another device such as a color-decoder, not by this product, because 525i and 625i signals include non-standard signals. however, if you use this product to recognize formats including the standard 525i and 625i, set ?a-sync = on?. otherwise, h/v freq det and h/v format may indicate incorrect value and vd-out may lock irregularly for 525i and 625i signals. refer to the ?application circuit 3 (system configuration)?, too.
TB1305FG, tb1308fg 2007-07-11 14 sync separation level the sync separation level is changed according to the ratio of h-sync width to one line and the connected resistance. typical sync separation levels for each format are as follows. then, vga-sep=1 for vga to uxga. hv-sep = 0 (low) hv-sep = 1 (high) format r = 1.2 k ? r = 1.5 k ? r = 1.8 k ? r = 1.2 k ? r = 1.5 k ? r = 1.8 k ? 625/50i 22 28 33 24 32 37 525/60i 22 28 34 24 31 37 625/50p 22 28 34 25 31 38 525/60p 21 27 32 24 30 36 1125/50i 31 39 45 40 49 54 1125/60i 26 33 39 34 43 50 750/50p 29 37 43 37 46 52 750/60p 24 31 37 32 40 47 1250/50i 25 32 37 32 41 47 1125/50p 36 45 51 45 54 58 1125/60p 31 39 45 39 49 55 vga/60 15 19 23 16 21 25 svga/60 15 18 22 16 20 24 xga/60 17 22 26 19 24 28 sxga/60 27 33 39 30 37 43 unit [%] ; where 286 mvp-p sync for 525/60i and 300 mvp-p sync for others for ?sync on g? signal, hd-out is not output during v-sync period because there is no h-sync during v-sync period. furthermore, for sync on g of xga input, hd-out disappears during active video period caused by unexpected lock of the internal v-blk. the format detection and sync separation performances are changed due to the separation level set by hv-sep, vga-sep setting and/or the connected resistance with sync-in pin. the careful evaluations are required to set the separation level under consideration of expected input conditions such as a suppressed sync input, an input with v-sag and apl (average picture level) fluctuations. note on sync input pin if the ac-coupling circuit is put before the sync-in pin, the picture on the screen may be not stable. this is because the sync separation circuit is unable to follow the dc level fluctuation caused by apl (average picture level) change in the input signal, and the hd and/or vd output is unable to synchronize the input. it is recommended to input signals via the dc-coupling buffer if necessary. for the dc level fluctuation caused by apl change, the sync separation ability may be improved to change the setting of hv-sep, vga-sep and/or changing the resister r. furthermore, adding a high-resistance around several m ? between sync-in pin and gnd (or vcc) may improve the sync separation ability. adding dc restoration circuit such as a clamp circuit can be also effective for the improvement of dc level fluctuation. also, refer to sync separation level descriptions.
TB1305FG, tb1308fg 2007-07-11 15 prefilter for ad converter the filter of the TB1305FG and tb1308fg can be used as a prefilter for ad converter. the cutoff frequency is controllable by i2cbus functions, filpass, f0-sw, bandwidth and fc half. the characteristics for cutoff frequency and delay time are as below. -50 -40 -30 -20 -10 0 10 1.e+04 1.e+05 1.e+06 1.e+07 1.e+08 frequency [hz] gain [db] f0 sw = low, bandwidth = min, fc half = on f0 sw = low, bandwidth = min f0 sw = high , bandwidt h = min f0 sw = high , bandwidt h = max figure. typical prefilter frequency characteristics 0 5 10 15 20 25 30 35 0 20406080100120 bandwidth data [dec] cutoff frequency (-3 db point) [mhz] f0 sw = low, fc half = on f0 sw = high, fc half = on f0 sw = low f0 sw = high figure. typical cutoff frequency (-3 db point) characteristics of prefilter due to bandwidth data. 10k 100k 1m 10m 100m
TB1305FG, tb1308fg 2007-07-11 16 0 20 40 60 80 100 120 140 160 180 200 0 20406080100120 bandwidt h d ata [dec] delay time [ns] f0 sw = low, fc half = on f0 sw = high, fc half = on f0 sw = low f0 sw = high figure. typical delay-time (group delay @ 1mhz) characteristics of prefilter due to bandwidth data. note on 1125/50p/60p input when 1125/50p and/or 60p signal are input, gain = 0(0db) and filpass = 0(on) are recommended due to the performance of the slew rate and cutoff frequency of the TB1305FG and tb1308fg circuits. a gain amplifier and/or a prefilter for 1125/50p/60p should be added as external circuits, if necessary. note on video output pins to conduct the video signal from the TB1305FG or tb1308fg to the following circuits, a buffer such as the one in the application circuits is required due to the drive capability of the tb 1305fg and tb1308fg being insufficient, especially for high-frequency components. the dc levels of the video output vary according to i 2 cbus functions, the apl of the input and temperature drift.therefore, the dc levels should be re-clamped in connected circuits such as ad converters. recommended crystal oscillator when a connected crystal oscillator is used for the xo, the following oscillation specifications are required. oscillation frequency (fundamental): 3.579545 mhz (for ntsc decoding) frequency tolerance: +/- 50 ppm external cw input into crystal oscillator pin instead of connecting a crystal oscillator, it is possible to input an external cw (continual wave) into pin 21 through a capacitor as below. the specifications required for cw input are as follows. input frequency (fundamental): 3.579545 mhz +/- 50 ppm input amplitude: 1.0 vp-p +/- 0.5 vp-p
TB1305FG, tb1308fg 2007-07-11 17 how to deal with unused pins unused pins should be dealt with as below. pins not mentioned below should be connected properly. pin no. pin name procedure pin no. pin name procedure 1 cr1/r1-in procedure 1 25 vd2-in procedure 4 2 line3-1 procedure 2 26 hd2-in procedure 4 3 cb1/b1-in procedure 1 27 address procedure 3 4 line2-1 procedure 2 28 sync-out procedure 3 5 y1/g1-in procedure 1 29 vd-out procedure 3 6 line1-1 procedure 2 30 hd-out procedure 3 7 nc procedure 2 32 y-out procedure 3 8 sync1-in procedure 3 34 cb-out procedure 3 9 sw line2 procedure 2 36 cr-out procedure 3 10 cr2/r2-in procedure 1 37 nc procedure 2 11 line3-2 procedure 2 38 sync3-in procedure 3 12 cb2/b2-in procedure 1 39 y3/g3-in procedure 1 13 line2-2 procedure 2 41 cb3/b3-in procedure 1 14 y2/g2-in procedure 1 42 dac2 procedure 3 15 line1-2 procedure 2 43 cr3/r3-in procedure 1 16 sync2-in procedure 3 45 c-in procedure 1 17 dac1 procedure 3 47 y-in procedure 1 23 vd1-in procedure 4 48 sw line1 procedure 2 24 hd1-in procedure 4 procedure 1: connect a 1 f capacitor between this pin and gnd. procedure 2: connect to gnd. procedure 3: leave open. procedure 4: connect a 10 k ? resister between this pin and gnd. note: pins 38, 39, 41 and 43 are nc pins for the TB1305FG. of these, any unused pins should be dealt with as in ?procedure 2?.
TB1305FG, tb1308fg 2007-07-11 18 how to start the i 2 cbus how to send bus data after power on is described below. use software to handle the procedure. 1. turn power on. 2. transmit all write data. how to transmit/receive via the i 2 cbus slave address: can be changed using pin 27. pin 27-gnd: d8 h /d9 h pin 27-open: da h /db h a6 a5 a4 a3 a2 a1 a0 w/r a6 a5 a4 a3 a2 a1 a0 w/r 1 1 0 1 1 0 0 0/1 1 1 0 1 1 0 1 0/1 pin 27-vcc: dc h /dd h a6 a5 a4 a3 a2 a1 a0 w/r 1 1 0 1 1 1 0 0/1 start and stop conditions bit transmission acknowledgement sda from transmitter low impedance at bit 9 only clock pulse for acknowledgement s high impedance at bit 9 1 8 9 sda from receiver scl from master sda scl s start condition p stop condition sda scl sda must not be changed sda may be changed
TB1305FG, tb1308fg 2007-07-11 19 data transmit format 1 data transmit format 2 data receive format to receive data, the master transmitter changes to a receiver immediately after the first acknowledgement. the slave receiver changes to a transmitter. the end condition is always created by the master. optional data transmit format (automatic increment mode) in this way, sub-addresses are automatically incremented from the specified sub-address and data are set. i 2 cbus conditions parameter symbol min. typ. max. unit low level input voltage v il 0 ? 1.1 v high level input voltage v ih 2.8 ? h-vcc v hysteresis of schmitt trigger inputs v hys ? 0.7 ? v low level output voltage at 3 ma sink current v ol1 0 ? 0.6 v input current each i/o pin with an input voltage between 0.1 vdd and 0.9 vdd i i -10 ? 10 a capacitance for each i/o pin c i ? ? 10 pf scl clock frequency f scl 0 ? 400 khz hold time start condition t hd;sta 0.6 ? ? s low period of scl clock t low 1.3 ? ? s high period of scl clock t high 0.6 ? ? s set-up time for a repeated start condition t su;sta 0.6 ? ? s data hold time t hd;dat 50 ? ? ns data set-up time t su;dat 100 ? ? ns set-up time for stop condition t su;sto 0.6 ? ? s bus free time between a stop and start condition t buf 1.3 ? ? s note: this parameter is not tested during production and is provided only as information to assist the design of applications. s slave address 0 a transmit data 1 a sub address a transmit data n a sub address a p ?????? ?????? s slave address 0 a transmit data a sub address a p 7-bit msb s: start condition 8-bit msb a: acknowledgement 8-bit msb p: end condition s slave address 1 a receive data n receive data 1 a p 7-bit msb 8-bit msb msb ????????? s slave address a transmit data n ???? transmit data 1 a p 7-bit msb 8-bit msb 0 sub address 7-bit msb a 1 8-bit msb
TB1305FG, tb1308fg 2007-07-11 20 absolute maximum ratings (ta = 25c) characteristic symbol rating unit supply voltage v ccmax 6.0 v input pin voltage v in gnd ? 0.3 ~ vcc + 0.3 v y or sync input amplitude (pins 5, 8, 14, 16, 38, 39, 47) (pins 38, 39 are for the tb1308fg only.) y in 2.0 vp-p power dissipation p d (note 5) 1136 mw power dissipation reduction rate 1/ ja 9.1 mw/ c operating temperature t opr ? 20 ~ 75 c storage temperature t stg ? 55 ~ 150 c note 5: refer to the figure below. note 6: handle pins 7 and 37 of the TB1305FG and tb1308fg with special care. these ics are sensitive to electrostatic discharge and surge impulse. install the product correctly. otherwise, it may result in break down, damage and/or degradation to the product or equipment. the absolute maximum ratings of a semiconductor device are a set of specified parameter values that must not be exceeded during operation, even for an instant. if any of these ratings are exceeded during operation, the electrical characteristics of the device may be irreparably altered, in which case the reliability and lifetime of the device can no longer be guaranteed. moreover, operations with exceeded ratings may cause breakdown, damage and/or degradation in other equipment. applications using the device should be designed so that no maximum rating will ever be exceeded under any operating conditions. before using, creating and/or producing designs, refer to and comply with the precautions and conditions set forth in these documents. ambient temperature ta (c) power consumption reduction ratio p d (mw) 0 150 25 75 0 682 1136 figure. p d - ta curve
TB1305FG, tb1308fg 2007-07-11 21 operating conditions characteristic description min. typ. max. unit pins 31, 46 4.7 5.0 5.3 supply voltage (v cc ) pin 22; supply power from h vcc (pin 31) via a resistor. 3.1 3.3 3.5 v y signal input amplitude pins 5, 8, 14, 16, 38, 39, 47; with sync ? 1.0 ? v p-p g signal input amplitude pins 8, 16, 38; with sync ? 1.0 ? v p-p pins 5, 14, 39 0 ? 60 y signal input frequency pin 47 0 ? 8 mhz chroma signal input amplitude pin 45 ? 0.3 2 v p-p dc voltage of chroma input pin pin 45 ? ? 3.6 v cb, cr, pb, pr signal input amplitude pins 1, 3, 10, 12, 41, 43; 100% color bar signal ? 0.7 ? v p-p cb, cr, pb, pr signal input frequency pins 1, 3, 10, 12, 41, 43 0 ? 60 mhz r, g, b signal input amplitude pins 1, 3, 5, 10, 12, 14, 39, 41, 43; 100% white signal without sync ? 0.7 ? v p-p r, g, b signal input frequency pins 1, 3, 5, 10, 12, 14, 39, 41, 43, 39, 41, 43 0 ? 60 mhz hd, vd signal input amplitude pins 23, 24, 25, 26 1.0 ? 2.0 v p-p hd input frequency pins 24, 26 for freq counter 0 ? 85 khz vd input frequency pins 23, 25 for freq counter 44 ? 3500 hz h 3.5 5.0 c-vcc m 1.4 2.2 2.4 line1,3 pins 2, 6, 11, 15 l ? gnd 0.6 v h 1.4 2.2 c-vcc line2 pins 4, 13 l ? gnd 0.6 v h 1.4 5.0 c-vcc line detection input voltage sw line pins 9, 48 l ? gnd 0.6 v 88/89 h ? gnd 0.6 da/db h pin open address switching voltage pin 27 dc/dd h 3.5 c-vcc c-vcc v sda input current pin 18 ? ? 3 ma remark: supply power to all vcc pins (pins 22, 31 and 46). note: pins 38, 39, 41 and 43, as y/cb/cr/sync3-in, are available for the tb1308fg only. pins 38, 39, 41 and 43 of the TB1305FG are nc pins.
TB1305FG, tb1308fg 2007-07-11 22 electrical characteristics (unless otherwise specified, c and h v cc = 5 v, d v cc = 3.3 v, ta = 25c, i 2 cbus data: preset values) current consumption pin name symbol test conditions min typ. max unit c v cc (pin 46) i ccc ? 30.0 38.0 46.0 h v cc (pin 31) i cch ? 4.5 6.0 7.5 d v cc (pin 22) i ccd resistance to 5 v; r = 150 ? 8.5 10.5 12.5 ma pin voltage (test condition: no signal input) pin no. pin name symbol test conditions min typ. max unit 1 cr1/r1-in v 1 ? 2.6 2.7 2.8 2 line3-1 v 2 ? 4.8 ? ? 3 cb1/b1-in v 3 ? 2.6 2.7 2.8 4 line2-1 v 4 ? 4.8 ? ? 5 y1/g1-in v 5 ? 1.95 2.1 2.25 6 line1-1 v 6 ? 4.8 ? ? 8 sync1-in v 8 ? 1.4 1.75 2.1 9 sw line2 v 9 ? 4.8 ? ? 10 cr2/r2-in v 10 ? 2.6 2.7 2.8 11 line3-2 v 11 ? 4.8 ? ? 12 cb2/b2-in v 12 ? 2.6 2.7 2.8 13 line2-2 v 13 ? 4.8 ? ? 14 y2/g2-in v 14 ? 1.95 2.1 2.25 15 line1-2 v 15 ? 4.8 ? ? 16 sync2-in v 16 ? 1.4 1.75 2.1 21 xtal v 21 ? 3.7 3.85 4.0 22 dig vcc v 22 resistance to 5 v; r = 150 ? 3.2 3.35 3.5 23 vd1-in v 23 ? 1.2 1.45 1.7 24 hd1-in v 24 ? 1.2 1.45 1.7 25 vd2-in v 25 ? 1.2 1.45 1.7 26 hd2-in v 26 ? 1.2 1.45 1.7 27 address v 27 pin open 1.8 2.0 2.2 32 y-out v 32 ? 0.3 1.0 1.7 34 cb-out v 34 ? 1.5 1.95 2.4 35 vf0adj v 35 ? 2.2 2.5 2.8 36 cr-out v 36 ? 1.5 1.95 2.4 38 sync3-in v 38 for the tb1308fg only 1.4 1.75 2.1 39 y3/g3-in v 39 for the tb1308fg only 1.95 2.1 2.25 40 bias fil v 40 ? 1.6 1.8 2.0 41 cb3/b3-in v 41 for the tb1308fg only 2.6 2.7 2.8 43 cr3/r3-in v 43 for the tb1308fg only 2.6 2.7 2.8 45 c-in v 45 ? 1.6 1.7 1.8 47 y-in v 47 ? 1.95 2.1 2.25 48 sw line1 v 48 ? 4.8 ? ? v
TB1305FG, tb1308fg 2007-07-11 23 video block characteristic symbol test conditions min typ. max unit sync-tip clamp mode vdsync 1.40 1.65 ? bias mode vdbias filpass = 1, bandwidth = max 1.40 1.65 ? input dynamic range chroma input vdchrm pin 45 1.40 1.65 ? vp-p gain = 0 gfoffg0 -1.0 -0.5 0 gain = 1 gfoffg6 filpass = 0, input = 0.2vp-p 10 khz 5.0 5.5 6.0 gain = 0 gfong0 -0.5 0 0.5 i/o gain gain = 1 gfong6 filpass = 1, f0 sw = 0, bandwidth = min, input = 0.2 vp-p 10 khz 5.5 6.0 6.5 db gain = 0 fg0 70 90 110 i/o frequency characteristic 1 gain = 1 fg6 filpass = 0, -3 db point, note 7 60 80 100 mhz bandwidth = max flmax 18.4 20.5 22.6 bandwidth = cnt flcnt 11.4 12.7 14.0 i/o frequency characteristic 2 bandwidth = min flmin filpass = 1, gain = 0, f0 sw = 1, -3 db point, note 7 3.7 4.2 4.7 mhz bandwidth = max fhmax 27.9 31.0 34.1 bandwidth = cnt fhcnt 21.6 24.0 26.4 i/o frequency characteristic 3 bandwidth = min fhmin filpass = 1, gain = 0, f0 sw = 0, -3 db point, note 7 14.6 16.3 18.0 mhz bandwidth = max fhflmax 9.2 10.3 11.4 bandwidth = cnt fhflcnt 5.7 6.4 7.1 i/o frequency characteristic 4 bandwidth = min fhflmin filpass = 1, gain = 0, f0 sw = 1, fc half = 1, -3 db point, note 7 1.85 2.1 2.35 mhz bandwidth = max fhfhmax 13.9 15.5 17.1 bandwidth = cnt fhfhcnt 10.8 12 13.2 i/o frequency characteristic 5 bandwidth = min fhfhmin filpass = 1, gain = 0, f0 sw = 0, fc half = 1, -3 db point, note 7 7.3 8.2 9.1 mhz gain = 0 fdg0 -10 0 10 differential 1 of frequency characteristic among 3 outputs gain = 1 fdg6 filpass = 0, -3 db point, note 7 -10 0 10 mhz bandwidth = max fdhmax -0.90 0 0.90 bandwidth = cnt fdhcnt -0.54 0 0.54 differential 2 of frequency characteristic among 3 outputs bandwidth = min fdhmin filpass = 1, f0 sw = 1, -3 db point, note 7 -0.18 0 0.18 mhz bandwidth = max fdhmax -1.30 0 1.30 bandwidth = cnt fdhcnt -1.05 0 1.05 differential 3 of frequency characteristic among 3 outputs bandwidth = min fdhmin filpass = 1, f0 sw = 0, -3 db point, note 7 -0.70 0 0.70 mhz gain = 0 tdg0 ? 5 10 i/o delay time 1 gain = 1 tdg6 filpass = 0, 1 mhz, note 7 ? 5 10 ns bandwidth = max tdlmax 18 23 28 bandwidth = cnt tdlcnt 29 34 39 i/o delay time 2 bandwidth = min tdlmin filpass = 1, gain = 0, f0 sw = 1, 1 mhz, note 7 85 95 105 ns bandwidth = max tdhmax 10 15 20 bandwidth = cnt tdhcnt 15 20 25 i/o delay time 3 bandwidth = min tdhmin filpass = 1, gain = 0, f0 sw = 0, 1 mhz, note 7 22 27 32 ns bandwidth = max tdhflmax 35 40 45 bandwidth = cnt tdhflcnt 58 65 72 i/o delay time 4 bandwidth = min tdhflmin filpass = 1, gain = 0, f0 sw = 1, fc half = 1, 1 mhz, note 7 170 190 210 ns
TB1305FG, tb1308fg 2007-07-11 24 characteristic symbol test conditions min typ. max unit bandwidth = max tdhfhmax 22 27 32 bandwidth = cnt tdhfhcnt 29 34 39 i/o delay time 5 bandwidth = min tdhfhmin filpass = 1, gain = 0, f0 sw = 0, fc half = 1, 1 mhz, note 7 45 50 55 ns gain = 0 tddg0 -10 0 10 differential 1 of delay time among 3 outputs gain = 1 tddg6 filpass = 0, 1 mhz, note 7 -10 0 10 ns bandwidth = max tddhmax -10 0 10 bandwidth = cnt tddhcnt -10 0 10 differential 2 of delay time among 3 outputs bandwidth = min tddhmin filpass = 1, f0 sw = 1, 1 mhz, note 7 -10 0 10 ns bandwidth = max tddhmax 0 10 20 bandwidth = cnt tddhcnt 10 20 30 differential 3 of delay time between y and cb/cr outputs bandwidth = min tddhmin filpass = 1, f0 sw = 0, fc half = 1, 1 mhz, note 7 35 45 55 ns bandwidth = max tddhmax -10 0 10 bandwidth = cnt tddhcnt -10 0 10 differential 4 of delay time between cb and cr outputs bandwidth = min tddhmin filpass = 1, f0 sw = 0, fc half = 1, 1 mhz, note 7 -10 0 10 ns mute mode attenuation gmute 30 mhz sin wave input, note 7 ? ? -50 db crosstalk among inputs gcrs 30 mhz sin wave input, note 7 ? ? -50 db note 7: this parameter is not tested during production and is provided only as information to assist the design of applications . synchronization block (test condition: a-sync = 1 (on)) characteristic symbol test conditions min typ max unit vsepl1 hv-sep = 0, 286 mvp-p sync, note 7 24 28 32 525/60i vseph1 hv-sep = 1, 286 mvp-p sync, note 7 27 31 35 % vsepl2 hv-sep = 0, 0.3 vp-p sync, note 7 30 34 38 1125/60i vseph2 hv-sep = 1, 0.3 vp-p sync, note 7 40 44 48 % vsepl3 hv-sep = 0, vga-sep = 1, 0.3 vp-p sync, note 7 14 18 22 h/v-sync separation level svga/60 vseph3 hv-sep = 1, vga-sep = 1, 0.3 vp-p sync, note 7 16 20 24 % threshold amplitude for hd input vthhd sync sw = 100 0.8 ? ? vp-p threshold amplitude for vd input vthvdn sync sw = 100 0.9 ? ? vp-p vhdh high level 3.2 3.4 3.5 hd-out voltage vhdl low level ? 0.1 0.4 v thdw0 hd width = 0 1.55 1.65 1.75 hd-out width thdw1 hd width = 1 0.55 0.65 0.75 us h sync-in to hd-out thdp1 sync-sw = 000, 1125/60p input 130 150 170 ns hd-out phase hd-in to hd-out thdp2 sync-sw = 100, note 7 23 28 32 ns
TB1305FG, tb1308fg 2007-07-11 25 characteristic symbol test conditions min typ. max unit vvdh high level 3.2 3.4 3.5 vd-out voltage vvdl low level ? 0.1 0.4 v sync sep tvdws separated vd-out ? 290 ? us 1250i odd tvdwodd ? 285 ? 1250i even tvdweven when 1250i input ? 270 ? us free-run 1 tvdwfi free-run vd-out in interlace mode ? 4 ? vd-out width free-run 2 tvdwfp free-run vd-out in progressive mode ? 8 ? h tvdp1 625/50i input 0.15 0.20 0.26 tvdp2 525/60i input 0.15 0.20 0.26 tvdp3 625/50p input 0.15 0.20 0.26 tvdp4 525/60p input 0.15 0.20 0.26 tvdp5 1125/50i input 0.15 0.20 0.26 tvdp6 1125/60i input 0.15 0.20 0.26 tvdp7 750/50p input 0.15 0.20 0.26 tvdp8 750/60p input 0.15 0.20 0.26 tvdp9 1125/50p input 0.10 0.15 0.20 tvdp10 1125/60p input 0.15 0.20 0.26 tvdp11 vga/60 input 0.15 0.20 0.26 tvdp12 svga/60 input 0.15 0.20 0.26 tvdp13 xga input 0.15 0.20 0.26 tvdp14 sxga input 0.15 0.20 0.26 v sync-in to vd-out tvdp15 uxga input 0.15 0.20 0.26 h h sync-in to vd-out tvdp16 1250/50i input, h sync-in to vd-out 330 340 350 ns vd-out phase vd-in to vd-out tvdp17 sync-sw=100, note 7 23 28 32 ns hv-sep = 0 vsupvl ? ? 52 minimum amplitude for suppressed v-sync to separate hv-sep = 1 vsupvh suppressed h/v-sync input, without picture, note 7 ? ? 48 % vsoh high level 3.2 3.4 3.5 sync out voltage vsol low level ? 0.1 0.4 v
TB1305FG, tb1308fg 2007-07-11 26 characteristic symbol test conditions min typ. max unit fh156 hv freq = 0000, s mode = 1 ? 15.564 ? fh157 hv freq = 0001, s mode = 1 ? 15.701 ? fh312 hv freq = 0010, s mode = 1 ? 31.401 ? fh315 hv freq = 0011, s mode = 1 ? 31.401 ? fh281 hv freq = 0100, s mode = 1 ? 27.966 ? fh337 hv freq = 0101, s mode = 1 ? 33.771 ? fh375 hv freq = 0110, s mode = 1 ? 37.288 ? fh450 hv freq = 0111, s mode = 1 ? 44.746 ? fh1250 hv freq = 1000, s mode = 1 ? 31.401 ? fh379 hv freq = 1001, s mode = 1 ? 37.288 ? fh640 hv freq = 1010, s mode = 1 ? 63.923 ? fh750 hv freq = 1011, s mode = 1 ? 74.577 ? dummy hd-out frequency fh562 hv freq = 1100, s mode = 1 ? 55.932 ? khz fv625i hv freq = 0000, s mode = 1 ? 312.5 ? fv525i hv freq = 0001, s mode = 1 ? 262.5 ? fv625p hv freq = 0010, s mode = 1 ? 625 ? fv525p hv freq = 0011, s mode = 1 ? 525 ? fv1125i5 hv freq = 0100, s mode = 1 ? 562.5 ? fv1125i6 hv freq = 0101, s mode = 1 ? 562.5 ? fv750p5 hv freq = 0110, s mode = 1 ? 750 ? fv750p6 hv freq = 0111, s mode = 1 ? 750 ? fv1250io hv freq = 1000, s mode = 1, odd ? 624.5 ? fv1250ie hv freq = 1000, s mode = 1, even ? 625.5 ? fvsvga hv freq = 1001, s mode = 1 ? 628 ? fvsxga hv freq = 1010, s mode = 1 ? 1066 ? fvuxga hv freq = 1011, s mode = 1 ? 1250 ? dummy vd-out frequency fv1125p5 hv freq = 1100, s mode = 1 ? 1125 ? h others tvdphs1 0.15 0.2 0.26 vd phs delay phase 1125/50p tvdphs2 no input, s mode = 1, vd phs = 1 0.1 0.15 0.2 h l ? m vln1lm 0.8 1.0 1.2 line1 detection threshold m ? h vln1mh pin 6, 15 2.8 3.0 3.2 line2 detection threshold l ? h vln2lh pin 4, 13 0.8 1.0 1.2 l ? m vln3lm 0.8 1.0 1.2 line3 detection threshold m ? h vln3mh pin 2, 11 2.8 3.0 3.2 sw line detection threshold l ? h vlnslh pin 9, 48 0.8 1.0 1.2 v input impedance of line input pin zline pin 2,4,6,9,11,13,15,48, note 7 120 150 ? k ? vdach high level 4.8 5.0 ? dac1,2 output voltage vdacl low level ? 0.2 0.4 v test mode threshold voltage vontest pin 45, turned-on voltage for test mode 3.6 ? ? v
TB1305FG, tb1308fg 2007-07-11 27 test circuit 1 2 3 4 5 6 7 8 9 10 11 12 13 14 38 37 36 35 34 33 32 31 30 29 TB1305FG/tb1308fg 15 16 17 18 19 20 21 22 23 24 25 26 27 28 48 47 46 45 44 43 42 41 40 39 line1-2 sync2-in dac1 sda scl dig gnd xtal dig vcc vd1-in hd1-in y3/g3-in bias fil cb3/b3-in dac2 cr3/r3-in c gnd c-in c vcc y-in sw line1 0.1f 0.1f 1.5k 0.1f 10k 470 + 3.579545mhz 0.01f 47f 4.7f 1f 100 100 + 10k 1f 100pf 1f 1f 1f 1f + 0.01f 47f hd1-in vd1-in dac1-out 1/2w 150 y3-in cb3-in cr3-in dac2-out c-in y-in vcc 5v 75 75 75 a b 75 75 scl sda 470 75 75 10pf c15 c16 r16 r17 r18a r19a x21 c21 ce22 r22 c22 ce23 r23a r23b ce24 r24a r24b l3 c39 r39 r41 c41 ce40 r42 r43 c43 c45 r45 sw1 ce46 l46 r47 c46 c47 c48 q32,q34,q36=2sa562tm components in the test circuits are only used to obtain and confirm the device characteristics. these components and circuits do not warrant to prevent the application equipment from malfunction or failure.
TB1305FG, tb1308fg 2007-07-11 28 application circuit 1 (TB1305FG: typical values) input video signals, which are driven with low impedance. the application circuits shown in this document are examples provided for reference purposes only. thorough evaluation is required in the mass production design phase. by furnishing these examples of application circuits, toshiba does not grant the use of any industrial property rights.
TB1305FG, tb1308fg 2007-07-11 29 application circuit 2 (tb1308fg: typical values) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 38 37 36 35 34 33 32 31 30 29 tb1308fg 15 16 17 18 19 20 21 22 23 24 25 26 27 28 48 47 46 45 44 43 42 41 40 39 line1-2 sync2-in dac1 sda scl dig gnd xtal dig vcc vd1-in hd1-in y3/g3-in bias fil cb3/b3-in dac2 cr3/r3-in c gnd c-in c vcc y-in sw line1 0.1f 0.1f 1.5k 0.1f 10k 470 470 + 10pf 3.579545mhz 0.01f 47f 4.7f 1f 100 100 + 10k 1f 100pf 1f 1f 1f 1f + 0.01f 47f input1 (d-pin 1) input2 (d-pin 2) hd1-in vd1-in scl sda dac1-out 1/2w 150 y3-in cb3-in cr3-in dac2-out c-in y-in vcc 5v input video signals, which are driven with low impedance. the application circuits shown in this document are examples provided for reference purposes only. thorough evaluation is required in the mass production design phase. by furnishing these examples of application circuits, toshiba does not grant the use of any industrial property rights.
TB1305FG, tb1308fg 2007-07-11 30 application circuit 3 (system configuration) (1) for non-standard signals such as cvbs, yc (s-video), 525i, 625i or so. the TB1305FG and tb1308fg cannot be used for non-standard signals such as weak strength signals, ghost signals and so on. therefore, these signals should be dealt with through the use of another device such as a color-decoder which is capable of handling these signals. in such cases, the signal switcher and the video circuits of the TB1305FG and tb1308fg can be used. the TB1305FG and tb1308fg cannot distinguish between component and rgb video. the different kinds of input signal should be separated through the use of different signal-specific input pins; for example, specific-purpose pins for rgb video input only or component video input only. (2) for standard component video (smpte standard) and standard rgb video (vesa standard) the TB1305FG and tb1308fg can detect a format type for standard signal inputs. the application circuits shown in this document are examples provided for reference purposes only. thorough evaluation is required in the mass production design phase. by furnishing these examples of application circuits, toshiba does not grant the use of any industrial property rights. tb1305/08 tb1305/08
TB1305FG, tb1308fg 2007-07-11 31 package dimensions p-qfp48-1014-0.80 unit: mm weight: 0.83 g (typ.)
TB1305FG, tb1308fg 2007-07-11 32 appendix: comparison table of the family 1) pin functions pin no. TB1305FG tb1308fg pin 38 nc sync3-in pin 39 nc y3/g3-in pin 41 nc cb3/b3-in pin 43 nc cr3/r3-in 2) write bus functions name data TB1305FG tb1308fg ycbcr sw 11 not available y3/cb3/cr3 010 not available sync3 110 hd1/vd1/not available hd1/vd1/sync3 sync sw 111 hd2/vd2/not available hd2/vd2/sync3 3) read bus functions name TB1305FG tb1308fg version 00: TB1305FG 01: tb1308fg
TB1305FG, tb1308fg 2007-07-11 33 about solderability, following conditions were confirmed ? solderability (1) use of sn-37pb solder bath solder bath temperature = 230c dipping time = 5 seconds the number of times = once use of r-type flux (2) use of sn-3.0ag-0.5cu solder bath solder bath temperature = 245c dipping time = 5 seconds the number of times = once use of r-type flux restrictions on product use ? the information contained herein is subject to change without notice. 021023_d ? toshiba is continually working to improve the quality an d reliability of its products. nevertheless, semiconductor devices in general can malfunction or fail due to their inhe rent electrical sensitivity and vulnerability to physical stress. it is the responsibility of the buyer, when utilizing toshiba products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such toshiba products could cause loss of human life, bodily injury or damage to property. in developing your designs, please ensure that toshiba products are used within specified operating ranges as set forth in the most recent toshiba products specifications. also, please keep in mind the precautions and conditions set forth in the ?handling guide for semiconductor devices,? or ?toshiba semiconductor reliability handbook? etc. 021023_a ? the toshiba products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). these toshiba products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (?unintended usage?). unintended usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc. unintended usage of toshiba products listed in this document shall be made at the customer?s own risk. 021023_b ? the products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or sale are prohibited under any applicable laws and regulations. 060106_q ? the information contained herein is presented only as a guide for the applications of our products. no responsibility is assumed by toshiba for any infringements of patents or other rights of the third parties which may result from its use. no license is granted by implication or otherwise under any patents or other rights of toshiba or the third parties. ? please use this product in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances. toshiba assumes no liability for damage or losses occurring as a result of noncompliance with applicable laws and regulations. ? the products described in this document are subject to the foreign exchange and foreign trade control laws.

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